From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 24 Dec 2014 14:08:06 +0000 (+0100)
Subject: command: remove returns to IDLE state (will be better to add a timeout for a transfer... 
X-Git-Tag: 24jan2021_ls180~2572^2~71
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7efaef485fabda0243536b67d0b97205a2c0217b;p=litex.git

command: remove returns to IDLE state (will be better to add a timeout for a transfer and reset the fsm).
---

diff --git a/lib/sata/command/__init__.py b/lib/sata/command/__init__.py
index 9c7e35cf..925ef08f 100644
--- a/lib/sata/command/__init__.py
+++ b/lib/sata/command/__init__.py
@@ -125,8 +125,6 @@ class SATACommandRX(Module):
 				If(test_type("DMA_ACTIVATE_D2H"),
 					dma_activate.eq(1),
 					NextState("WAIT_WRITE_REG_D2H")
-				).Else(
-					NextState("IDLE") # Generate an error
 				)
 			)
 		)
@@ -135,8 +133,6 @@ class SATACommandRX(Module):
 			If(transport.source.stb,
 				If(test_type("REG_D2H"),
 					NextState("PRESENT_WRITE_RESPONSE")
-				).Else(
-					NextState("IDLE") # Generate an error
 				)
 			)
 		)
@@ -154,8 +150,6 @@ class SATACommandRX(Module):
 				transport.source.ack.eq(0),
 				If(test_type("DATA"),
 					NextState("PRESENT_READ_DATA")
-				).Else(
-					NextState("IDLE") # Generate an error
 				)
 			)
 		)
@@ -174,8 +168,6 @@ class SATACommandRX(Module):
 			If(transport.source.stb,
 				If(test_type("REG_D2H"),
 					NextState("PRESENT_READ_RESPONSE")
-				).Else(
-					NextState("IDLE") # Generate an error
 				)
 			)
 		)