From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 8 Feb 2022 14:43:03 +0000 (+0000)
Subject: cross-link to gitlab rst files
X-Git-Tag: opf_rfc_ls005_v1~3220
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7efaf2c0a888c2326b3b7cb21fdac4945b49429f;p=libreriscv.git

cross-link to gitlab rst files
---

diff --git a/docs/learning_nmigen.mdwn b/docs/learning_nmigen.mdwn
index 795a7c72b..1c14cd264 100644
--- a/docs/learning_nmigen.mdwn
+++ b/docs/learning_nmigen.mdwn
@@ -1,8 +1,9 @@
 # Learning nmigen
 
 * Link to the mail thread: <http://lists.libre-soc.org/pipermail/libre-soc-dev/2021-October/003858.html>
-* Links to community <https://nmigen.info/nmigen/latest/tutorial.html>
-* Useful counter tutorial (gtkwave and verilog) for latest nmigen <https://nmigen.info/nmigen/latest/start.html>
+* Links to community <https://gitlab.com/nmigen/nmigen/blob/master/docs/tutorial.rst>
+* Useful counter tutorial (gtkwave and verilog) for latest nmigen
+  <https://gitlab.com/nmigen/nmigen/blob/master/docs/start.rst>
 * Robert Baruch's nmigen tutorials are really good:
   <https://github.com/RobertBaruch/nmigen-tutorial>
 * <https://github.com/GuzTech/ulx3s-nmigen-examples>
@@ -15,7 +16,8 @@
 
 ## Testbench, GTKWave, Verilog Output 
 
-nMigen code for counter and testbench here: <https://nmigen.info/nmigen/latest/start.html>
+nMigen code for counter and testbench here:
+<https://gitlab.com/nmigen/nmigen/blob/master/docs/start.rst>
 
 1. Create a file called "up_counter.py" containing the 16-bit up counter code from "Implementing a counter" section.