From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 30 May 2018 12:17:36 +0000 (+0200)
Subject: Update examples/cmos/counter.ys to use "synth" command
X-Git-Tag: yosys-0.8~80
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7f0548c16f64bd0c4e3bd85744cfdcf9494b4829;p=yosys.git

Update examples/cmos/counter.ys to use "synth" command

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---

diff --git a/examples/cmos/counter.ys b/examples/cmos/counter.ys
index a784f3465..d0b093667 100644
--- a/examples/cmos/counter.ys
+++ b/examples/cmos/counter.ys
@@ -1,11 +1,12 @@
-
 read_verilog counter.v
 read_verilog -lib cmos_cells.v
 
-proc;; memory;; techmap;;
-
+synth
 dfflibmap -liberty cmos_cells.lib
-abc -liberty cmos_cells.lib;;
+abc -liberty cmos_cells.lib
+opt_clean
+
+stat -liberty cmos_cells.lib
 
 # http://vlsiarch.ecen.okstate.edu/flows/MOSIS_SCMOS/latest/cadence/lib/tsmc025/signalstorm/osu025_stdcells.lib
 # dfflibmap -liberty osu025_stdcells.lib
@@ -13,4 +14,3 @@ abc -liberty cmos_cells.lib;;
 
 write_verilog synth.v
 write_spice synth.sp
-