From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 20 Apr 2019 11:49:33 +0000 (+0100)
Subject: improve ControlBase.ports enumeration of its o_data and i_data
X-Git-Tag: ls180-24jan2020~1216
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7f1066d06416debdf793398e7ce31c35309785b1;p=ieee754fpu.git

improve ControlBase.ports enumeration of its o_data and i_data
---

diff --git a/src/add/singlepipe.py b/src/add/singlepipe.py
index ca01e858..967f2d43 100644
--- a/src/add/singlepipe.py
+++ b/src/add/singlepipe.py
@@ -650,12 +650,16 @@ class ControlBase:
                ]
         if hasattr(self.p.i_data, "ports"):
             res += self.p.i_data.ports()
-        else:
+        elif isinstance(self.p.i_data, Sequence):
             res += self.p.i_data
+        else:
+            res.append(self.p.i_data)
         if hasattr(self.n.o_data, "ports"):
             res += self.n.o_data.ports()
-        else:
+        elif isinstance(self.n.o_data, Sequence):
             res += self.n.o_data
+        else:
+            res.append(self.n.o_data)
         return res
 
     def _elaborate(self, platform):