From: Francisco Jerez Date: Sun, 1 May 2016 03:47:49 +0000 (-0700) Subject: i965/fs: Remove pre-Gen7 register allocation class micro-optimization. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7f10d3983b1ef1bafbbb694c29430556122f4536;p=mesa.git i965/fs: Remove pre-Gen7 register allocation class micro-optimization. This was trying to save some one-time init on pre-Gen7 hardware under the assumption that one would only ever need 1, 2, 4 and 8-wide registers on those platforms. However nothing guarantees that those will be the only VGRF sizes used after lowering and optimization. In some cases we may end up with a temporary of different size being allocated (e.g. by SIMD lowering to zip or unzip a multi-component register region of a logical send instruction), and there is no guarantee that they will be optimized away before register allocation (especially since the compute_to_mrf coalescing pass is rather... lacking...). Instead just allocate classes for all possible VGRF sizes up to MAX_VGRF_SIZE to avoid a crash in pq_test() when we encounter a variable of any other size. Reviewed-by: Jason Ekstrand --- diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp index 7fdedc084c5..cd84dc22254 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp @@ -102,26 +102,11 @@ brw_alloc_reg_set(struct brw_compiler *compiler, int dispatch_width) * Additionally, on gen5 we need aligned pairs of registers for the PLN * instruction, and on gen4 we need 8 contiguous regs for workaround simd16 * texturing. - * - * So we have a need for classes for 1, 2, 4, and 8 registers currently, - * and we add in '3' to make indexing the array easier for the common case - * (since we'll probably want it for texturing later). - * - * And, on gen7 and newer, we do texturing SEND messages from GRFs, which - * means that we may need any size up to the sampler message size limit (11 - * regs). */ - int class_count; + const int class_count = MAX_VGRF_SIZE; int class_sizes[MAX_VGRF_SIZE]; - - if (devinfo->gen >= 7) { - for (class_count = 0; class_count < MAX_VGRF_SIZE; class_count++) - class_sizes[class_count] = class_count + 1; - } else { - for (class_count = 0; class_count < 4; class_count++) - class_sizes[class_count] = class_count + 1; - class_sizes[class_count++] = 8; - } + for (unsigned i = 0; i < MAX_VGRF_SIZE; i++) + class_sizes[i] = i + 1; memset(compiler->fs_reg_sets[index].class_to_ra_reg_range, 0, sizeof(compiler->fs_reg_sets[index].class_to_ra_reg_range));