From: lkcl <lkcl@web>
Date: Sun, 29 Aug 2021 12:29:02 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~280
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7f14444176e05003580b2562e4da36d9a169d704;p=libreriscv.git

---

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index f84257b0e..914595e8d 100644
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -481,7 +481,14 @@ Thus, logically, we may set the following rule:
 
 Examples of the former type:
 
-* crand, cror, crnor. These all are 5-bit (BA, BB, BC).
+* crand, cror, crnor. These all are 5-bit (BA, BB, BT). The bit
+  to be tested against `inv` is the one selected by `BT`
+* mcrf. This has only 3-bit (BF, BFA). In order to select the
+  bit to be tested, the alternative FFirst encoding must be used.
+
+This limits sv.mcrf in that it may not use the `VLi` (VL inclusive)
+Mode. This is unfortunste but unavoidable due to encoding pressure
+on SVP64.
 
 # pred-result mode