From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Thu, 21 Feb 2019 01:36:57 +0000 (-0800)
Subject: ABC -> ABC9
X-Git-Tag: working-ls180~1237^2~284
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7f26043caf6f9810d8541caaa57151ec8fb539a1;p=yosys.git

ABC -> ABC9
---

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 3f0072d24..4b045cbea 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -532,7 +532,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 
 		ifs.close();
 
-		log_header(design, "Re-integrating ABC results.\n");
+		log_header(design, "Re-integrating ABC9 results.\n");
 		RTLIL::Module *mapped_mod = mapped_design->modules_["\\netlist"];
 		if (mapped_mod == NULL)
 			log_error("ABC output file does not contain a module `netlist'.\n");