From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 29 Jun 2019 09:35:49 +0000 (+0100)
Subject: add comments
X-Git-Tag: ls180-24jan2020~956
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7f2e4e9cdcd604cdfb11da22380a630c7155fa70;p=ieee754fpu.git

add comments
---

diff --git a/src/ieee754/fpdiv/div1.py b/src/ieee754/fpdiv/div1.py
index 5ceff1fe..c314c36c 100644
--- a/src/ieee754/fpdiv/div1.py
+++ b/src/ieee754/fpdiv/div1.py
@@ -39,10 +39,13 @@ class FPDivStage1Mod(Elaboratable):
         m = Module()
 
         # XXX TODO, actual DIV code here.  this class would be
-        # "step two" and is the main "chain".  tons of these needed.
-        # here is where Q and R are used, TODO: those need to be in
+        # here is where Q and R are used, TODO: Q/REM (etc) need to be in
         # FPDivStage0Data.
 
+        # NOTE: this does ONE step of conversion.  it does NOT do
+        # MULTIPLE stages of Q/REM processing.  it *MUST* be PURE
+        # combinatorial and one step ONLY.
+
         # store intermediate tests (and zero-extended mantissas)
         am0 = Signal(len(self.i.a.m)+1, reset_less=True)
         bm0 = Signal(len(self.i.b.m)+1, reset_less=True)