From: Cesar Strauss <cestrauss@gmail.com>
Date: Mon, 6 Jul 2020 11:12:59 +0000 (-0300)
Subject: Assert n.ready_i at the beginning of the cycle
X-Git-Tag: div_pipeline~162^2~38
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7f4015949019da87d10cc12889dd2ed1525bc88b;p=soc.git

Assert n.ready_i at the beginning of the cycle

This simulates the common case where we are ready for the
result as soon as the ALU delivers it.
The special case for the zero-delay operation is no longer
needed.
---

diff --git a/src/soc/experiment/alu_hier.py b/src/soc/experiment/alu_hier.py
index fd5add20..828511b6 100644
--- a/src/soc/experiment/alu_hier.py
+++ b/src/soc/experiment/alu_hier.py
@@ -392,24 +392,7 @@ def run_op(dut, a, b, op, inv_a=0):
     yield dut.op.invert_a.eq(inv_a)
     yield dut.n.ready_i.eq(0)
     yield dut.p.valid_i.eq(1)
-
-    # if valid_o rose on the very first cycle, it is a
-    # zero-delay ALU
-    yield Settle()
-    vld = yield dut.n.valid_o
-    if vld:
-        # special case for zero-delay ALU
-        # we must raise ready_i first, since the combinatorial ALU doesn't
-        # have any storage, and doesn't dare to assert ready_o back to us
-        # until we accepted the output data
-        yield dut.n.ready_i.eq(1)
-        result = yield dut.o
-        yield
-        yield dut.p.valid_i.eq(0)
-        yield dut.n.ready_i.eq(0)
-        yield
-        return result
-
+    yield dut.n.ready_i.eq(1)
     yield
 
     # wait for the ALU to accept our input data
@@ -423,11 +406,8 @@ def run_op(dut, a, b, op, inv_a=0):
         yield
 
     # latch the result and lower read_i
-    yield dut.n.ready_i.eq(1)
     result = yield dut.o
-    yield
     yield dut.n.ready_i.eq(0)
-    yield
 
     return result