From: lkcl <lkcl@web>
Date: Sun, 15 May 2022 16:14:14 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2225
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7f493b0656dfd164e518c6e4de87c0f1c6351472;p=libreriscv.git

---

diff --git a/openpower/sv/bitmanip.mdwn b/openpower/sv/bitmanip.mdwn
index 52b70aeca..a6b421f71 100644
--- a/openpower/sv/bitmanip.mdwn
+++ b/openpower/sv/bitmanip.mdwn
@@ -261,6 +261,25 @@ uint_xlen_t intabs(uint_xlen_t rs1, uint_xlen_t rs2) {
 }
 ```
 
+## abs-accumulate
+
+required for the [[sv/av_opcodes]], these are needed for motion estimation.
+both are overwrite on RS.
+
+```
+uint_xlen_t uintabsacc(uint_xlen_t rs, uint_xlen_t ra, uint_xlen_t rb) {
+     return rs + (src1 > src2) ? (src1-src2) : (src2-src1)
+}
+uint_xlen_t intabsacc(uint_xlen_t rs, int_xlen_t ra, int_xlen_t rb) {
+     return rs + (src1 > src2) ? (src1-src2) : (src2-src1)
+}
+```
+
+For SVP64 these use EXTRA2 and allow Twin Elwidths. The reason is so
+that the Register used as an Accumulator (RS) may have its own
+Element Width Override. This allows e.g. a 16 bit accumulator for 8 bit
+differences.
+
 # shift-and-add
 
 Power ISA is missing LD/ST with shift, which is present in both ARM and x86.