From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 8 Feb 2014 18:13:19 +0000 (+0100)
Subject: Fixed bug in collecting of RD_TRANSPARENT parameter in memory_collect
X-Git-Tag: yosys-0.2.0~37
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7f52c18a22e85b0a2db17511b4617534395aacfb;p=yosys.git

Fixed bug in collecting of RD_TRANSPARENT parameter in memory_collect
---

diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc
index 40504d781..6fe5e162c 100644
--- a/passes/memory/memory_collect.cc
+++ b/passes/memory/memory_collect.cc
@@ -160,6 +160,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
 
 	sig_rd_clk_enable.optimize();
 	sig_rd_clk_polarity.optimize();
+	sig_rd_transparent.optimize();
 
 	assert(sig_rd_clk.width == rd_ports);
 	assert(sig_rd_clk_enable.width == rd_ports && sig_rd_clk_enable.is_fully_const());