From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 17 Mar 2022 12:52:50 +0000 (+0000)
Subject: initialise bitslip with a specific value rather than an incrementor
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7f70b441fb40a05c097db1f0941fba85ca784080;p=gram.git

initialise bitslip with a specific value rather than an incrementor
---

diff --git a/gram/common.py b/gram/common.py
index 183f9ce..7c5f449 100644
--- a/gram/common.py
+++ b/gram/common.py
@@ -71,7 +71,7 @@ class BitSlip(Elaboratable):
     def __init__(self, dw, rst=None, slp=None, cycles=1):
         self.i = Signal(dw)
         self.o = Signal(dw)
-        self.rst = Signal() if rst is None else rst
+        #self.rst = Signal() if rst is None else rst
         self.slp = Signal() if slp is None else slp
         self.dw = dw
         self.cycles = cycles
@@ -82,10 +82,11 @@ class BitSlip(Elaboratable):
         vcount = self.cycles * self.dw
         value = Signal(vcount.bit_length())
 
-        with m.If(self.rst):
-            sync += value.eq(0)
-        with m.Elif(self.slp):
-            sync += value.eq(value+1)
+        #with m.If(self.rst):
+        #    sync += value.eq(0)
+        #with m.Elif(self.slp):
+        #    sync += value.eq(value+1)
+        comb += value.eq(self.slp)
 
         # Shift Register using input i.
         r = Signal((self.cycles+1)*self.dw, reset_less=True)
diff --git a/gram/phy/ecp5ddrphy.py b/gram/phy/ecp5ddrphy.py
index 5a9c8f6..b31e19e 100644
--- a/gram/phy/ecp5ddrphy.py
+++ b/gram/phy/ecp5ddrphy.py
@@ -133,6 +133,7 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
         self.rdly = []
         self.rdly += [bank.csr(3, "rw", name="rdly_p0")]
         self.rdly += [bank.csr(3, "rw", name="rdly_p1")]
+        self.bitslip = bank.csr(3, "rw") # phase-delay on read
 
         self._bridge = self.bridge(data_width=32, granularity=8, alignment=2)
         self.bus = self._bridge.bus
@@ -478,7 +479,7 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
                         io_B=self.pads.dq.io[j])
                 ]
                 # shift-register delay on the incoming read data
-                dq_i_bs = BitSlip(4, Const(0), Const(0), cycles=1)
+                dq_i_bs = BitSlip(4, Const(0), cycles=1)
                 m.submodules['dq_i_bitslip_%d' % j] = dq_i_bs
                 dq_i_bs_o = Signal(4, name="dq_i_bs_o_%d" % j)
                 dq_i_bs_o_d = Signal(4, name="dq_i_bs_o_d_%d" % j)