From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 10 Mar 2020 16:27:00 +0000 (+0000)
Subject: comments explaining what alu_hier.py does
X-Git-Tag: div_pipeline~1728
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7f7d2424239ca85cf9cf1dc0f908de28db441ab6;p=soc.git

comments explaining what alu_hier.py does
---

diff --git a/src/soc/experiment/alu_hier.py b/src/soc/experiment/alu_hier.py
index 9659059c..f1606198 100644
--- a/src/soc/experiment/alu_hier.py
+++ b/src/soc/experiment/alu_hier.py
@@ -1,3 +1,14 @@
+"""*Experimental* ALU: based on nmigen alu_hier.py, includes branch-compare ALU
+
+This ALU is *deliberately* designed to add in (unnecessary) delays into
+different operations so as to be able to test the 6600-style matrices
+and the CompUnits.  Countdown timers wait for (defined) periods before
+indicating that the output is valid
+
+A "real" integer ALU would place the answers onto the output bus after
+only one cycle (sync)
+"""
+
 from nmigen import Elaboratable, Signal, Module, Const, Mux
 from nmigen.cli import main
 from nmigen.cli import verilog, rtlil