From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 5 Jun 2021 18:07:40 +0000 (+0100)
Subject: disallow adding verilog files
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7f9016c7d485eabd6d68756e3c3bbf68ff71c178;p=soc-cocotb-sim.git

disallow adding verilog files
---

diff --git a/.gitignore b/.gitignore
index 3a8cbad..ff14265 100644
--- a/.gitignore
+++ b/.gitignore
@@ -2,3 +2,4 @@
 __pycache__/
 sim_build_*/
 results_*.xml
+*.v