From: Dmitry Selyutin <ghostmansd@gmail.com>
Date: Sat, 10 Sep 2022 06:07:27 +0000 (+0300)
Subject: power_insn: refactor register verbose assembly
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7f909fda4f363432e0050deb920055eb3c675ade;p=openpower-isa.git

power_insn: refactor register verbose assembly
---

diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py
index f705406a..d2f65580 100644
--- a/src/openpower/decoder/power_insn.py
+++ b/src/openpower/decoder/power_insn.py
@@ -632,7 +632,8 @@ class RegisterOperand(DynamicOperand):
         (vector, value, span) = self.spec(insn=insn, record=record)
 
         if verbosity >= Verbosity.VERBOSE:
-            yield f"{indent}{self.name}"
+            mode = "vector" if vector else "scalar"
+            yield f"{indent}{self.name} ({mode})"
             yield f"{indent}{indent}{int(value):0{value.bits}b}"
             yield f"{indent}{indent}{', '.join(span)}"
             if isinstance(insn, SVP64Instruction):
@@ -642,8 +643,6 @@ class RegisterOperand(DynamicOperand):
                 else:
                     etype = repr(record.etype).lower()
                     yield f"{indent}{indent}{etype}{extra_idx!r}"
-                yield f"{indent}type"
-                yield f"{indent}{indent}{'vector' if vector else 'scalar'}"
         else:
             vector = "*" if vector else ""
             yield f"{vector}{prefix}{int(value)}"