From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 13 Apr 2023 09:08:46 +0000 (+0100)
Subject: add ldst-shifted-postinc notes into ls012 v2
X-Git-Tag: opf_rfc_ls010_v1~17
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7f9247424422718a3c64bbb2efeb510ece02636d;p=libreriscv.git

add ldst-shifted-postinc notes into ls012 v2
---

diff --git a/openpower/sv/rfc/ls012.mdwn b/openpower/sv/rfc/ls012.mdwn
index 671f2e5e6..e2e19ae9f 100644
--- a/openpower/sv/rfc/ls012.mdwn
+++ b/openpower/sv/rfc/ls012.mdwn
@@ -80,6 +80,8 @@ Audio/Visual, High-Performance Compute, GPU workloads and DSP.
 * 4 - INT<->FP mv [[ls006]]
 * 19 - GPR LD/ST-PostIncrement-Update (saves hugely in hot-loops) [[ls011]]
 * ~12 - FPR LD/ST-PostIncrement-Update (ditto) [[ls011]]
+* 19 - GPR LD/ST-Shifted-PostIncrement-Update (saves hugely in hot-loops) [[ls011]]
+* ~12 - FPR LD/ST-Shifted-PostIncrement-Update (ditto) [[ls011]]
 * 26 - GPR LD/ST-Shifted (again saves hugely in hot-loops) [[ls004]]
 * 11 - FPR LD/ST-Shifted (ditto) [[ls004]]
 * 2 - Float-Load-Immediate (always saves one LD L1/2/3 D-Cache op) [[ls002]]
@@ -376,6 +378,15 @@ Whilst this is a "solution" it is less than ideal, and the opportunity
 exists now with the EXT2xx Primary Opcodes to correct this and bring
 Power ISA up a level.
 
+Where things begin to get more than a little hairy is if both
+Post-Increment *and* Shifted are included.  If SVP64 keeps one
+single bit (/pi) dedicated in the `RM.Mode` field then this
+problem ges away, at the cost of reducing SVP64's effectiveness,
+but at least a stunning **24** Primary Opcodes (there are only
+32 in EXT2xx) would not disappear overnight.
+Mostly the Post-Increment-and-Shifted set are included to illustrate
+the options and have a formal record of the evluation, for Due Diligence.
+
 ## Shift-and-add (and LD/ST Indexed-Shift)
 
 Shift-and-Add are proposed in [[ls004]].  They mitigate the need to add
@@ -394,6 +405,8 @@ Also included because it is important to see the quantity of instructions:
 LD/ST-Indexed-Shifted.  Across Update variants, Byte-reverse variants,
 Arithmetic and FP, the total is a slightly-eye-watering **37**
 instructions, only ameliorated by the fact that they are all 9-bit XO.
+When it comes to Shifted-Postincrement the number of Primary Opcodes
+needed in EXT2xx comes to 24 which is most of them.
 The upside as far as adding them is concerned is that existing hardware
 will already have amalgamated pipelines with very few actual back-end
 (Micro-Coded) internal operations (likely just two: one load, one store).
@@ -403,6 +416,10 @@ is not hard.
 *(Readers unfamiliar with Micro-coding should look at the Microwatt VHDL
 source code)*
 
+When it comes to LD/ST-Shifted-Postincrement the sheer number particularly
+Primary Opcodes needed in EXT2xx makes for a compelling case to prioritise
+Shift-and-Add.
+
 \newpage{}
 
 # Vectorisation: SVP64 and SVP64Single