From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 13 Jun 2019 16:15:30 +0000 (-0700)
Subject: Update CHANGELOG with "synth -abc9"
X-Git-Tag: working-ls180~1237^2~130
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7f9d2d18251c3bec667993c744b568bbbe1a75ce;p=yosys.git

Update CHANGELOG with "synth -abc9"
---

diff --git a/CHANGELOG b/CHANGELOG
index 139f71672..44e32c6a8 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -20,6 +20,7 @@ Yosys 0.8 .. Yosys 0.8-dev
     - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
     - Added "synth_xilinx -abc9" (experimental)
     - Added "synth_ice40 -abc9" (experimental)
+    - Added "synth -abc9" (experimental)
     - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"