From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 24 Apr 2022 13:05:37 +0000 (+0100)
Subject: list of hyperrams not just one
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7f9fbc9e73e0786aae516cbe8ccea15913846315;p=ls2.git

list of hyperrams not just one
---

diff --git a/src/ls2.py b/src/ls2.py
index 283eb41..993186f 100644
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -795,8 +795,8 @@ class DDR3SoC(SoC, Elaboratable):
         # and at the moment that's just UART tx/rx.
         ports = []
         ports += [self.uart.tx_o, self.uart.rx_i]
-        if hasattr(self, "hyperram"):
-            ports += list(self.hyperram.ports())
+        for hr in self.hyperramL
+            ports += list(hr.ports())
         if hasattr(self, "ddrphy"):
             if hasattr(self.ddrphy, "pads"): # real PHY
                 ports += list(self.ddrphy.pads.fields.values())