From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Wed, 18 Mar 2015 23:24:30 +0000 (+0100)
Subject: fhdl/verilog: fix dummy signal initial event
X-Git-Tag: 24jan2021_ls180~2099^2~161
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7fa1cd72a8d354409087dc8b001a5eeb7a4385d2;p=litex.git

fhdl/verilog: fix dummy signal initial event
---

diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index ee420662..bc050441 100644
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -184,7 +184,8 @@ def _printcomb(f, ns, display_run):
 		syn_on = "// synthesis translate_on\n"
 		dummy_s = Signal(name_override="dummy_s")
 		r += syn_off
-		r += "reg " + _printsig(ns, dummy_s) + " = 1'd0;\n"
+		r += "reg " + _printsig(ns, dummy_s) + ";\n"
+		r += "initial " + ns.get_name(dummy_s) + " <= 1'd0;\n"
 		r += syn_on
 
 		groups = group_by_targets(f.comb)