From: Nicolai Hähnle <nicolai.haehnle@amd.com>
Date: Thu, 10 Jan 2019 22:21:46 +0000 (+0100)
Subject: amd/common/vi+: enable SMEM loads with GLC=1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7fbd48fdc0848c7c6e2b5a9a78e69f9c3b08e365;p=mesa.git

amd/common/vi+: enable SMEM loads with GLC=1

Only on LLVM 8.0+, which supports the new intrinsic.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
---

diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c
index 4d7f15901e3..6aa96ee86d4 100644
--- a/src/amd/common/ac_llvm_build.c
+++ b/src/amd/common/ac_llvm_build.c
@@ -1230,8 +1230,8 @@ ac_build_buffer_load(struct ac_llvm_context *ctx,
 	if (soffset)
 		offset = LLVMBuildAdd(ctx->builder, offset, soffset, "");
 
-	/* TODO: VI and later generations can use SMEM with GLC=1.*/
-	if (allow_smem && !glc && !slc) {
+	if (allow_smem && !slc &&
+	    (!glc || (HAVE_LLVM >= 0x0800 && ctx->chip_class >= VI))) {
 		assert(vindex == NULL);
 
 		LLVMValueRef result[8];
@@ -1245,7 +1245,11 @@ ac_build_buffer_load(struct ac_llvm_context *ctx,
 				HAVE_LLVM >= 0x0800 ? "llvm.amdgcn.s.buffer.load.f32"
 						    : "llvm.SI.load.const";
 			unsigned num_args = HAVE_LLVM >= 0x0800 ? 3 : 2;
-			LLVMValueRef args[3] = {rsrc, offset, ctx->i32_0};
+			LLVMValueRef args[3] = {
+				rsrc,
+				offset,
+				glc ? ctx->i32_1 : ctx->i32_0,
+			};
 			result[i] = ac_build_intrinsic(ctx, intrname,
 						       ctx->f32, args, num_args,
 						       AC_FUNC_ATTR_READNONE |