From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 8 Apr 2020 13:52:39 +0000 (+0100)
Subject: whitespace and add extra "constructive listening" section to Mission
X-Git-Tag: convert-csv-opcode-to-binary~2903
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7fc77a970abf615a46dc702a1dc6a85e08b01a34;p=libreriscv.git

whitespace and add extra "constructive listening" section to Mission
---

diff --git a/The_Mission.mdwn b/The_Mission.mdwn
index 02c277866..25879d681 100644
--- a/The_Mission.mdwn
+++ b/The_Mission.mdwn
@@ -1,14 +1,21 @@
-> We believe a computer should be safe to use, and this starts with a safe processor.
+> We believe a computer should be safe to use, and this starts with a
+> safe processor.
 
 # The Mission
 
- - give mass volume appliance manufacturers an alternative to expensive un-auditable chips.
- - maximize the degree of trust a customer can place in their processor. 
+- give mass volume appliance manufacturers an alternative to expensive
+   un-auditable chips.
+- maximize the degree of trust a customer can place in their processor.
 
 # The Means:
 
-- provide the customer the **freedom to study, modify, and redistribute** the full SoC source from HDL and boot loader to down to the VLSI.
-- engage in **full transparency** at every level of the development, right from the inception through to delivery of silicon.  no exceptions.
+- provide the customer the **freedom to study, modify, and redistribute**
+  the full SoC source from HDL and boot loader to down to the VLSI.
+- engage in **full transparency** at every level of the development,
+  right from the inception through to delivery of silicon.  no exceptions.
+- listen to **constructive input** from world-leading industry experts,
+  engineers and enthusiasts alike, in real-time, without NDAs creating
+  artificial barriers to communication and hampering success.
 
 # The Market:
 
@@ -21,7 +28,13 @@
  - CV capable flight controller for lightweight drones
  - whatever you want
 
-# The Machine:
+# The Machines:
+
+- our first target (Oct 2020): a single-core dual-issue 180nm 64-bit
+  "demo" QFP chip that will also be a saleable product in the "Embedded"
+  space (Arduino, STM32F, Ingenic jz4720).
+- a full quad core SoC: 800mhz, dual issue, 4-wide FP32, Hybrid CPU /
+  GPU / VPU [and later an ML inference core], comparable to the Allwinner
+  64 in capability.
+- Products based on customer - and client - driven needs and requirements
 
-- our first target (Oct 2020): a single-core dual-issue 180nm 64-bit "demo" QFP chip that will also be a saleable product in the "Embedded" space (Arduino, STM32F, Ingenic jz4720).
-- a full quad core SoC: 800mhz, dual issue, 4-wide FP32, Hybrid CPU / GPU / VPU [and later an ML inference core], comparable to the Allwinner 64 in capability.