From: whitequark <whitequark@whitequark.org>
Date: Fri, 7 Dec 2018 18:48:06 +0000 (+0000)
Subject: write_verilog: correctly map RTLIL `sync init`.
X-Git-Tag: yosys-0.9~381^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7fe770a441a129c509fd4da04b60ada942a28bc8;p=yosys.git

write_verilog: correctly map RTLIL `sync init`.
---

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index dde03f920..922b4c44c 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1352,6 +1352,8 @@ void dump_process(std::ostream &f, std::string indent, RTLIL::Process *proc, boo
 
 		if (sync->type == RTLIL::STa) {
 			f << stringf("%s" "always @* begin\n", indent.c_str());
+		} else if (sync->type == RTLIL::STi) {
+			f << stringf("%s" "initial begin\n", indent.c_str());
 		} else {
 			f << stringf("%s" "always @(", indent.c_str());
 			if (sync->type == RTLIL::STp || sync->type == RTLIL::ST1)