From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 21 Jul 2020 14:23:04 +0000 (+0100)
Subject: set ISACaller.msr rather than namespace[MSR]
X-Git-Tag: semi_working_ecp5~653
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7feec03ab04179912d812ed0e18d4144fd7ce8b5;p=soc.git

set ISACaller.msr rather than namespace[MSR]
---

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 5c8d6b6f..85b8aa5c 100644
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -341,7 +341,7 @@ class ISACaller:
         self.dec2 = decoder2
 
     def TRAP(self, trap_addr=0x700, trap_bit=PI.TRAP):
-        print ("TRAP:", hex(trap_addr))
+        print ("TRAP:", hex(trap_addr), hex(self.namespace['MSR'].value))
         # store CIA(+4?) in SRR0, set NIA to 0x700
         # store MSR in SRR1, set MSR to um errr something, have to check spec
         self.spr['SRR0'].value = self.pc.CIA.value
@@ -353,13 +353,13 @@ class ISACaller:
         # in figure 66 p1065 V3.0B and the table figure 65 p1063 set these
         # bits appropriately.  however it turns out that *for now* in all
         # cases (all trap_addrs) the exact same thing is needed.
-        self.namespace['MSR'][63-MSR.SF] = 1
-        self.namespace['MSR'][63-MSR.EE] = 0
-        self.namespace['MSR'][63-MSR.PR] = 0
-        self.namespace['MSR'][63-MSR.IR] = 0
-        self.namespace['MSR'][63-MSR.DR] = 0
-        self.namespace['MSR'][63-MSR.RI] = 0
-        self.namespace['MSR'][63-MSR.LE] = 1
+        self.msr[63-MSR.SF] = 1
+        self.msr[63-MSR.EE] = 0
+        self.msr[63-MSR.PR] = 0
+        self.msr[63-MSR.IR] = 0
+        self.msr[63-MSR.DR] = 0
+        self.msr[63-MSR.RI] = 0
+        self.msr[63-MSR.LE] = 1
 
     def memassign(self, ea, sz, val):
         self.mem.memassign(ea, sz, val)