From: lkcl <lkcl@web>
Date: Thu, 16 Sep 2021 14:50:42 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~99
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7ff30c1f0e2c0570a8a8a60801171427560e5b2e;p=libreriscv.git

---

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index 2ab94e570..f6b221f4d 100644
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -36,7 +36,7 @@ to transfer the CRs in and out of an integer, where bitmanipulation
 may be performed to analyse the carry bits (including carry lookahead
 propagation) before continuing with further parallel additions.
 
-# v3.0B/v3.1B relevant instructions
+# v3.0B/v3.1 relevant instructions
 
 SV is primarily designed for use as an efficient hybrid 3D GPU / VPU /
 CPU ISA.