From: David Shah <dave@ds0.me>
Date: Mon, 18 Nov 2019 13:58:03 +0000 (+0000)
Subject: memory_collect: Copy attr from RTLIL::Memory to  cell
X-Git-Tag: working-ls180~943^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7ff5d6d30ae9f48376f0c6a98d8a5fa0831faf77;p=yosys.git

memory_collect: Copy attr from RTLIL::Memory to  cell

Signed-off-by: David Shah <dave@ds0.me>
---

diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc
index 6acbce62f..9dcb3f024 100644
--- a/passes/memory/memory_collect.cc
+++ b/passes/memory/memory_collect.cc
@@ -218,6 +218,10 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory)
 	mem->setPort("\\RD_DATA", sig_rd_data);
 	mem->setPort("\\RD_EN", sig_rd_en);
 
+	// Copy attributes from RTLIL memory to $mem
+	for (auto attr : memory->attributes)
+		mem->attributes[attr.first] = attr.second;
+
 	for (auto c : memcells)
 		module->remove(c);