From: lkcl <lkcl@web>
Date: Tue, 7 Jun 2022 16:06:58 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1920
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=800441312b9b212f72ba730a65522d001dd89138;p=libreriscv.git

---

diff --git a/openpower/sv/compliancy_levels.mdwn b/openpower/sv/compliancy_levels.mdwn
index 47fd91076..753b59589 100644
--- a/openpower/sv/compliancy_levels.mdwn
+++ b/openpower/sv/compliancy_levels.mdwn
@@ -20,7 +20,7 @@ instructions (REMAP), as well as for the entire SVP64 Prefix space.
 Summary of Compliancy Levels, each Level includes all lower levels:
 
 * **Ultra-embedded**: `setvl` instruction and context-switching of SVSTATE
-  into SVSRR1. Register Files as Standard Power ISA.
+  to/from SVSRR1. Register Files as Standard Power ISA.
 * **Embedded**: `svstep` instruction,
   and support for Hardware for-looping
   in both Horizontal-First and Vertical-First Mode as well as Predication
@@ -30,3 +30,7 @@ Summary of Compliancy Levels, each Level includes all lower levels:
   overrides, and all Modes (Saturation, Fail-First, Predicate-Result,
   Mapreduce/Iteration)
 * **3D/Advanced/Supercomputing**: REMAP capability
+
+These Levels constitute the minimum requirements. It is also permitted that any Level include any part of a higher Compliancy
+Level. An Embedded Level is permitted to have 128 GPRs, FPRs and CR Fields,
+but the Compliance Tests for Embedded will only test for 32.