From: whitequark <cz@m-labs.hk>
Date: Thu, 13 Dec 2018 02:35:46 +0000 (+0000)
Subject: back.rtlil: match shape of $mux ports A/B/Y.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=80076fa69196ca819dfe99cbbc253e05bdfec756;p=nmigen.git

back.rtlil: match shape of $mux ports A/B/Y.
---

diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py
index c008369..808ae32 100644
--- a/nmigen/back/rtlil.py
+++ b/nmigen/back/rtlil.py
@@ -349,14 +349,17 @@ class _ValueTransformer(xfrm.ValueTransformer):
         lhs_bits, lhs_sign = lhs.shape()
         rhs_bits, rhs_sign = rhs.shape()
         res_bits, res_sign = node.shape()
+        lhs_bits = rhs_bits = res_bits = max(lhs_bits, rhs_bits, res_bits)
+        lhs_wire = self.match_shape(lhs, lhs_bits, lhs_sign)
+        rhs_wire = self.match_shape(rhs, rhs_bits, rhs_sign)
         res = self.rtlil.wire(width=res_bits)
         self.rtlil.cell("$mux", ports={
-            "\\A": self(lhs),
-            "\\B": self(rhs),
+            "\\A": lhs_wire,
+            "\\B": rhs_wire,
             "\\S": self(sel),
             "\\Y": res,
         }, params={
-            "WIDTH": max(lhs_bits, rhs_bits, res_bits)
+            "WIDTH": res_bits
         })
         return res