From: Andrey Miroshnikov Date: Mon, 15 Nov 2021 19:08:23 +0000 (+0000) Subject: Added get_tristate JTAG connection X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=800e9b622f39a06547b6c63c0127135bc8a38bb1;p=pinmux.git Added get_tristate JTAG connection --- diff --git a/src/spec/testing_stage1.py b/src/spec/testing_stage1.py index 067c218..2adf184 100644 --- a/src/spec/testing_stage1.py +++ b/src/spec/testing_stage1.py @@ -281,13 +281,30 @@ class ASICPlatform(TemplatedPlatform): self._check_feature("single-ended tristate", pin, attrs, valid_xdrs=(0,), valid_attrs=None) + print (" get_tristate", pin, "port", port, port.layout) m = Module() + if pin.name in ['clk_0', 'rst_0']: # sigh + print("No JTAG chain in-between") + m.submodules += Instance("$tribuf", + p_WIDTH=pin.width, + i_EN=pin.oe, + i_A=self._invert_if(invert, pin.o), + o_Y=port, + ) + return m + (res, pin, port, attrs) = self.padlookup[pin.name] + io = self.jtag.ios[pin.name] + print (" pad", res, pin, port, attrs) + print (" pin", pin.layout) + print (" jtag", io.core.layout, io.pad.layout) m.submodules += Instance("$tribuf", p_WIDTH=pin.width, - i_EN=pin.oe, - i_A=self._invert_if(invert, pin.o), + i_EN=io.pad.oe, + i_A=self._invert_if(invert, io.pad.o), o_Y=port, ) + m.d.comb += io.core.o.eq(pin.o) + m.d.comb += io.core.oe.eq(pin.oe) return m def get_input_output(self, pin, port, attrs, invert):