From: lkcl <lkcl@web>
Date: Tue, 31 Aug 2021 15:18:30 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~270
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=801a5e59ee980e1fd97b18580468796943da060a;p=libreriscv.git

---

diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index 15869d0d3..395dce205 100644
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -1,16 +1,11 @@
-# TODO
+# Data-dependent fail-first on CR operations
 
-SVP64 RM `MODE` (includes `ELWIDTH` and `ELWIDTH_SRC` bits) for Branch
-Conditional:
+SVP64 RM `MODE` (includes `ELWIDTH` bits) for CR-based operations:
 
-| 4 | 5 | 6 | 7 | 19 | 20 |  21 | 22   23 |  description     |
-| - | - | - | - | -- | -- | --- |---------|----------------- |
-|ALL|LRu| / | / | 0  | 0  | /   |  SNZ sz | normal mode      |
-|ALL|LRu| / |VSb| 0  | 1  | VLI |  SNZ sz | VLSET mode       |
-|ALL|LRu|CTi| / | 1  | 0  | /   |  SNZ sz | CTR-test mode         |
-|ALL|LRu|CTi|VSb| 1  | 1  | VLI |  SNZ sz | CTR-test+VLSET mode   |
-
-# Data-dependent fail-first on CR operations (crand etc)
+| 4 | 5 | 19-20 |  21 | 22   23 |  description     |
+| - | - | ----- | --- |---------|----------------- |
+|dz |VLi| 01    | inv |  CR-bit | normal mode      |
+|sz |VLi| 01    | inv |  dz Rc1 | VLSET mode       |
 
 Operations that actually produce or alter CR Field as a result
 do not also in turn have an Rc=1 mode.  However it makes no