From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 7 Jul 2019 15:57:19 +0000 (+0100)
Subject: clarify if else
X-Git-Tag: ls180-24jan2020~889
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8023f4e3c8207696a3cd7625926f4e2fab0ef709;p=ieee754fpu.git

clarify if else
---

diff --git a/src/ieee754/div_rem_sqrt_rsqrt/core.py b/src/ieee754/div_rem_sqrt_rsqrt/core.py
index 245cd1c6..f87077df 100644
--- a/src/ieee754/div_rem_sqrt_rsqrt/core.py
+++ b/src/ieee754/div_rem_sqrt_rsqrt/core.py
@@ -357,7 +357,7 @@ class DivPipeCoreCalculateStage(Elaboratable):
         next_compare_rhs = Signal(radix, reset_less=True)
         l = []
         for i in range(radix):
-            next_flag = pass_flags[i + 1] if i + 1 < radix else 0
+            next_flag = pass_flags[i + 1] if (i + 1 < radix) else Const(0)
             flag = Signal(reset_less=True, name=f"flag{i}")
             test = Signal(reset_less=True, name=f"test{i}")
             # XXX TODO: check the width on this