From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 18 Jul 2019 22:22:00 +0000 (-0700)
Subject: Check if RHS is empty first
X-Git-Tag: working-ls180~1039^2~334
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=802470746c320676d61431d420e33d34c239da84;p=yosys.git

Check if RHS is empty first
---

diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index c2bec4c54..7a175123e 100644
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -11,6 +11,7 @@ match ffA
 	select ffA->type.in($dff, $dffe)
 	// DSP48E1 does not support clock inversion
 	select param(ffA, \CLK_POLARITY).as_bool()
+	filter !port(dsp, \A).remove_const().empty()
 	filter includes(port(ffA, \Q).to_sigbit_set(), port(dsp, \A).remove_const().to_sigbit_set())
 	optional
 endmatch
@@ -24,6 +25,7 @@ match ffB
 	select ffB->type.in($dff, $dffe)
 	// DSP48E1 does not support clock inversion
 	select param(ffB, \CLK_POLARITY).as_bool()
+	filter !port(dsp, \B).remove_const().empty()
 	filter includes(port(ffB, \Q).to_sigbit_set(), port(dsp, \B).remove_const().to_sigbit_set())
 	optional
 endmatch