From: clairexen Date: Thu, 9 Jul 2020 16:39:30 +0000 (+0200) Subject: Merge pull request #2244 from antmicro/logic X-Git-Tag: working-ls180~398 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=802671b22edbedda593d4c256423975786c581a3;p=yosys.git Merge pull request #2244 from antmicro/logic Add logic type support to parameters --- 802671b22edbedda593d4c256423975786c581a3