From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 18 May 2020 03:58:05 +0000 (+0100)
Subject: correct import after soc.fu move
X-Git-Tag: div_pipeline~1090
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=803b550147b4af3799dda4fd83bfa7e1696f839f;p=soc.git

correct import after soc.fu move
---

diff --git a/src/soc/fu/logical/main_stage.py b/src/soc/fu/logical/main_stage.py
index 39c2400d..06e1afbc 100644
--- a/src/soc/fu/logical/main_stage.py
+++ b/src/soc/fu/logical/main_stage.py
@@ -11,7 +11,7 @@ from soc.fu.logical.pipe_data import ALUInputData
 from soc.fu.alu.pipe_data import ALUOutputData
 from ieee754.part.partsig import PartitionedSignal
 from soc.decoder.power_enums import InternalOp
-from soc.countzero.countzero import ZeroCounter
+from soc.fu.countzero.countzero import ZeroCounter
 
 from soc.decoder.power_fields import DecodeFields
 from soc.decoder.power_fieldsn import SignalBitRange