From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 18 Dec 2021 01:56:21 +0000 (+0000)
Subject: ooo annoying, it is actually icache.ibus
X-Git-Tag: sv_maxu_works-initial~626
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=806de854e996ae2932db3f3000ec760efad37332;p=openpower-isa.git

ooo annoying, it is actually icache.ibus
---

diff --git a/src/openpower/test/runner.py b/src/openpower/test/runner.py
index 333bb117..cc91b75d 100644
--- a/src/openpower/test/runner.py
+++ b/src/openpower/test/runner.py
@@ -483,7 +483,7 @@ class TestRunnerBase(FHDLTestCase):
             default_mem = self.rom
             sim.add_sync_process(wrap(wb_get(dcache.bus,
                                              default_mem, "DCACHE")))
-            sim.add_sync_process(wrap(wb_get(icache.bus,
+            sim.add_sync_process(wrap(wb_get(icache.ibus,
                                              default_mem, "ICACHE")))
 
         with sim.write_vcd("issuer_simulator.vcd"):