From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 13 Feb 2019 11:36:47 +0000 (+0100)
Subject: Fix sign handling of real constants
X-Git-Tag: yosys-0.9~315
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=807b3c769733b8cf07f5b14674df41bd2788e09d;p=yosys.git

Fix sign handling of real constants

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 9531dd356..e66625228 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -942,16 +942,15 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 
 	// simply return the corresponding RTLIL::SigSpec for an AST_CONSTANT node
 	case AST_CONSTANT:
+	case AST_REALVALUE:
 		{
 			if (width_hint < 0)
 				detectSignWidth(width_hint, sign_hint);
-
 			is_signed = sign_hint;
-			return RTLIL::SigSpec(bitsAsConst());
-		}
 
-	case AST_REALVALUE:
-		{
+			if (type == AST_CONSTANT)
+				return RTLIL::SigSpec(bitsAsConst());
+
 			RTLIL::SigSpec sig = realAsConst(width_hint);
 			log_file_warning(filename, linenum, "converting real value %e to binary %s.\n", realvalue, log_signal(sig));
 			return sig;