From: lkcl <lkcl@web>
Date: Wed, 12 Oct 2022 10:37:21 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~87
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=808837856e45c724488c31b5437ebad33b58415c;p=libreriscv.git

---

diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn
index eb32548ed..8562d32c2 100644
--- a/openpower/sv/ldst.mdwn
+++ b/openpower/sv/ldst.mdwn
@@ -152,7 +152,13 @@ written out in quick succession to a memory-mapped peripheral from
 sequentially-numbered registers.
 
 Note that any memory location may be Cache-inhibited
-(Power ISA v.1, Book III, 1.6.1, p1033)
+(Power ISA v3.1, Book III, 1.6.1, p1033)
+
+*Programmer's Note: an immediate also with a Scalar source as
+a "VSPLAT" mode is simply not possible: there are not enough
+Mode bits. One single Scalar Load operation may be used instead, followed
+by any arithmetic operation (including a simple mv) in "Splat"
+mode.*
 
 **LD/ST Indexed**