From: Eddie Hung Date: Mon, 13 Jan 2020 17:43:57 +0000 (-0800) Subject: abc9: log which module is being operated on X-Git-Tag: working-ls180~849^2~35 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=808b388e34f3cededd450de35555476874cf2799;p=yosys.git abc9: log which module is being operated on --- diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 2ded1c162..2e3df773e 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -276,9 +276,11 @@ struct Abc9Pass : public ScriptPass run(stringf("write_xaiger -map %s/input.sym %s/input.xaig", tempdir_name.c_str(), tempdir_name.c_str())); int num_outputs = active_design->scratchpad_get_int("write_xaiger.num_outputs"); - log("Extracted %d AND gates and %d wires to a netlist network with %d inputs and %d outputs.\n", + + log("Extracted %d AND gates and %d wires from module `%s' to a netlist network with %d inputs and %d outputs.\n", active_design->scratchpad_get_int("write_xaiger.num_ands"), active_design->scratchpad_get_int("write_xaiger.num_wires"), + log_id(mod), active_design->scratchpad_get_int("write_xaiger.num_inputs"), num_outputs); if (num_outputs) { diff --git a/passes/techmap/abc9_exe.cc b/passes/techmap/abc9_exe.cc index c1687ef97..a2acfac91 100644 --- a/passes/techmap/abc9_exe.cc +++ b/passes/techmap/abc9_exe.cc @@ -168,10 +168,6 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe std::string wire_delay, std::string tempdir_name ) { - //FIXME: - //log_header(design, "Extracting gate netlist of module `%s' to `%s/input.xaig'..\n", - // module->name.c_str(), replace_tempdir(tempdir_name, tempdir_name, show_tempdir).c_str()); - std::string abc9_script; if (!lut_costs.empty())