From: Ben Widawsky <ben@bwidawsk.net>
Date: Mon, 8 Jul 2019 19:24:24 +0000 (-0700)
Subject: intel_synth: Make family explicit and match
X-Git-Tag: working-ls180~1183^2~5
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=809b94a67b0b666018b35536d4de327e99378a6f;p=yosys.git

intel_synth: Make family explicit and match

The help and code default to MAX10 for the family, however the couple of
if ladders defaulted to cycloneive. Fix this inconsistency and the next
patch will clean it up.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---

diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc
index 69f3b6334..9d5d593a4 100644
--- a/techlibs/intel/synth_intel.cc
+++ b/techlibs/intel/synth_intel.cc
@@ -176,8 +176,10 @@ struct SynthIntelPass : public ScriptPass {
 				run("read_verilog -sv -lib +/intel/cyclone10/cells_sim.v");
 			else if (check_label("family") && family_opt == "cycloneiv")
 				run("read_verilog -sv -lib +/intel/cycloneiv/cells_sim.v");
-			else
+			else if (check_label("family") && family_opt == "cycloneive")
 				run("read_verilog -sv -lib +/intel/cycloneive/cells_sim.v");
+			else
+				log_cmd_error("Invalid or not family specified: '%s'\n", family_opt.c_str());
 			// Misc and common cells
 			run("read_verilog -sv -lib +/intel/common/m9k_bb.v");
 			run("read_verilog -sv -lib +/intel/common/altpll_bb.v");
@@ -236,8 +238,10 @@ struct SynthIntelPass : public ScriptPass {
 				run("techmap -map +/intel/cyclone10/cells_map.v");
 			else if (family_opt == "cycloneiv")
 				run("techmap -map +/intel/cycloneiv/cells_map.v");
-			else
+			else if (family_opt == "cycloneive")
 				run("techmap -map +/intel/cycloneive/cells_map.v");
+			else
+				log_cmd_error("Invalid or not family specified: '%s'\n", family_opt.c_str());
 			run("dffinit -highlow -ff dffeas q power_up");
 			run("clean -purge");
 		}