From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 4 Nov 2021 19:07:37 +0000 (+0000)
Subject: write-ok is expected to stay valid *after* being set,
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=809cf2faa4450901779045cfaa89e69f70ed9f42;p=soc.git

write-ok is expected to stay valid *after* being set,
working out what is going on here
---

diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py
index 77cfa2d7..101f86cd 100644
--- a/src/soc/experiment/compalu_multi.py
+++ b/src/soc/experiment/compalu_multi.py
@@ -269,6 +269,7 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable):
             name = "data_r%d" % i
             lro = self.get_out(i)
             ok = Const(1, 1)
+            data_r_ok = Const(1, 1)
             if isinstance(lro, Record):
                 data_r = Record.like(lro, name=name)
                 print("wr fields", i, lro, data_r.fields)
@@ -276,9 +277,15 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable):
                 fname = find_ok(data_r.fields)
                 if fname:
                     ok = getattr(lro, fname)
+                    data_r_ok = getattr(data_r, fname)
+                # write-ok based on incoming output *and* whether the latched
+                # data was ok.
+                # XXX fails - wrok.append((ok|data_r_ok) & self.busy_o)
+                wrok.append(ok & self.busy_o)
             else:
+                # really should retire this but it's part of unit tests
                 data_r = Signal.like(lro, name=name, reset_less=True)
-            wrok.append(ok & self.busy_o)
+                wrok.append(ok & self.busy_o)
             with m.If(alu_pulse):
                 m.d.sync += data_r.eq(lro)
             with m.If(self.issue_i):