From: lkcl <lkcl@web>
Date: Thu, 13 Apr 2023 10:58:02 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls010_v1~14
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=80b14629635749f469344b2a6b252d99c440f16e;p=libreriscv.git

---

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index 95dbffd1e..69da11392 100644
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -178,7 +178,7 @@ need do is avoid
 use of SVP64 Prefixed instructions to perform the necessary
 save/restore of Simple-V Architectural State.
 This capability also allows nested function calls to be made from
-inside Vector loops, which is very rare for Vector ISAs.
+inside Vertical-First Vector loops, which is very rare for Vector ISAs.
 
 Strict Program Order is also preserved by the Parallel Reduction
 REMAP Schedule, but only at the cost of requiring the destination