From: Florent Kermarrec Date: Mon, 20 Jan 2020 11:10:00 +0000 (+0100) Subject: targets: use mem_region.origin instead of mem_map definition (prepare for automatic... X-Git-Tag: 24jan2021_ls180~725 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=80c3dc41d3d31e000095a395cec7476ba9e1b645;p=litex.git targets: use mem_region.origin instead of mem_map definition (prepare for automatic mem_region allocation) --- diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py index 4e463449..8bbfa3cd 100755 --- a/litex/boards/targets/arty.py +++ b/litex/boards/targets/arty.py @@ -94,8 +94,8 @@ class EthernetSoC(BaseSoC): dw = 32, interface = "wishbone", endianness = self.cpu.endianness) - self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") + self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") # timing constraints diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py index 30478c01..55cc272a 100755 --- a/litex/boards/targets/genesys2.py +++ b/litex/boards/targets/genesys2.py @@ -87,8 +87,8 @@ class EthernetSoC(BaseSoC): dw = 32, interface = "wishbone", endianness = self.cpu.endianness) - self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") + self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") # timing constraints diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py index 041c4b46..70b2f9fb 100755 --- a/litex/boards/targets/kc705.py +++ b/litex/boards/targets/kc705.py @@ -88,8 +88,8 @@ class EthernetSoC(BaseSoC): dw = 32, interface = "wishbone", endianness = self.cpu.endianness) - self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") + self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") # timing constraints diff --git a/litex/boards/targets/kcu105.py b/litex/boards/targets/kcu105.py index a6241173..36601746 100755 --- a/litex/boards/targets/kcu105.py +++ b/litex/boards/targets/kcu105.py @@ -123,8 +123,8 @@ class EthernetSoC(BaseSoC): dw = 32, interface = "wishbone", endianness = self.cpu.endianness) - self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") + self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") # timing constraints diff --git a/litex/boards/targets/netv2.py b/litex/boards/targets/netv2.py index 44a64d05..40e20071 100755 --- a/litex/boards/targets/netv2.py +++ b/litex/boards/targets/netv2.py @@ -90,8 +90,8 @@ class EthernetSoC(BaseSoC): dw = 32, interface = "wishbone", endianness = self.cpu.endianness) - self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") + self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") # timing constraints diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr.py index 8940ac4a..fa78b9d5 100755 --- a/litex/boards/targets/nexys4ddr.py +++ b/litex/boards/targets/nexys4ddr.py @@ -89,8 +89,8 @@ class EthernetSoC(BaseSoC): dw = 32, interface = "wishbone", endianness = self.cpu.endianness) - self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") + self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") # timing constraints diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py index 9773f9ac..4d261d3c 100755 --- a/litex/boards/targets/nexys_video.py +++ b/litex/boards/targets/nexys_video.py @@ -89,8 +89,8 @@ class EthernetSoC(BaseSoC): dw = 32, interface = "wishbone", endianness = self.cpu.endianness) - self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") + self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") # timing constraints diff --git a/litex/boards/targets/simple.py b/litex/boards/targets/simple.py index fa74077d..904959ed 100755 --- a/litex/boards/targets/simple.py +++ b/litex/boards/targets/simple.py @@ -48,8 +48,8 @@ class EthernetSoC(BaseSoC): # mac self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness, with_preamble_crc=False) - self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") + self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex/boards/targets/versa_ecp5.py b/litex/boards/targets/versa_ecp5.py index 412f1544..9951b798 100755 --- a/litex/boards/targets/versa_ecp5.py +++ b/litex/boards/targets/versa_ecp5.py @@ -114,8 +114,8 @@ class EthernetSoC(BaseSoC): # mac self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) - self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") + self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") # timing constraints diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py index ecf3edf6..36e13b1d 100755 --- a/litex/tools/litex_sim.py +++ b/litex/tools/litex_sim.py @@ -158,8 +158,8 @@ class SimSoC(SoCSDRAM): if with_etherbone: ethmac = ClockDomainsRenamer({"eth_tx": "ethphy_eth_tx", "eth_rx": "ethphy_eth_rx"})(ethmac) self.submodules.ethmac = ethmac - self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") + self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac")