From: Gabe Black <gabeblack@google.com>
Date: Thu, 9 Jan 2020 09:08:09 +0000 (-0800)
Subject: x86: Stop clearing RAX for BIST in initCPU.
X-Git-Tag: v19.0.0.0~112
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=80c5add40b096e29fa45d266104af54733f925f0;p=gem5.git

x86: Stop clearing RAX for BIST in initCPU.

This doesn't actually change any behavior since RAX was being zeroed
anyway, but since we don't and almost certainly never will have a BIST
and the BIST is optional even in real hardware, we can drop it and
simplify initCPU a little further.

This reduces x86's initCPU function to just an invocation of
InitInterrupt's invoke.

Change-Id: I56b1aae2c1a738ef7ffabcf648dd7d0fb819d4e0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24187
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
---

diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc
index b00e6867f..75f242d83 100644
--- a/src/arch/x86/utility.cc
+++ b/src/arch/x86/utility.cc
@@ -74,16 +74,7 @@ getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
 void
 initCPU(ThreadContext *tc, int cpuId)
 {
-    // This function is essentially performing a reset. The actual INIT
-    // interrupt does a subset of this, so we'll piggyback on some of its
-    // functionality.
-    InitInterrupt init(0);
-    init.invoke(tc);
-
-    // Set integer register EAX to 0 to indicate that the optional BIST
-    // passed. No BIST actually runs, but software may still check this
-    // register for errors.
-    tc->setIntReg(INTREG_RAX, 0);
+    InitInterrupt(0).invoke(tc);
 }
 
 void startupCPU(ThreadContext *tc, int cpuId)