From: Gabe Black <gblack@eecs.umich.edu>
Date: Mon, 27 Aug 2007 03:31:30 +0000 (-0700)
Subject: O3 CPU: Remove alignment check from dynamic instruction read/write functions.
X-Git-Tag: m5_2.0_beta4~172
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=80d51650c8bce1503e5ce3877f3bfe21d3e57d45;p=gem5.git

O3 CPU: Remove alignment check from dynamic instruction read/write functions.

--HG--
extra : convert_revision : e5d415b4bf79353ef3c9f4dc5af09ab4102c55fb
---

diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 362babeff..0f2a90bf6 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -847,12 +847,6 @@ BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
     req->setVirt(asid, addr, sizeof(T), flags, this->PC);
     req->setThreadContext(thread->readCpuId(), threadNumber);
 
-    if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() >
-        TheISA::VMPageSize) {
-        delete req;
-        return TheISA::genAlignmentFault();
-    }
-
     fault = cpu->translateDataReadReq(req, thread);
 
     if (req->isUncacheable())
@@ -909,12 +903,6 @@ BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
     req->setVirt(asid, addr, sizeof(T), flags, this->PC);
     req->setThreadContext(thread->readCpuId(), threadNumber);
 
-    if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() >
-        TheISA::VMPageSize) {
-        delete req;
-        return TheISA::genAlignmentFault();
-    }
-
     fault = cpu->translateDataWriteReq(req, thread);
 
     if (req->isUncacheable())