From: Udi Finkelstein <github@udifink.com>
Date: Tue, 5 Jun 2018 09:15:59 +0000 (+0300)
Subject: reg_wire_error test needs the -sv flag so it is run via a script so it had to be... 
X-Git-Tag: yosys-0.8~37^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=80d9d15f1c4b73ee73172b06fd2c8c55703aea54;p=yosys.git

reg_wire_error test needs the -sv flag so it is run via a script so it had to be moved out of the tests/simple dir that only runs Verilog files
---

diff --git a/tests/simple/reg_wire_error.v b/tests/simple/reg_wire_error.v
deleted file mode 100644
index ab461b95a..000000000
--- a/tests/simple/reg_wire_error.v
+++ /dev/null
@@ -1,40 +0,0 @@
-module sub_mod(input i_in, output o_out);
-assign o_out = i_in;
-endmodule
-
-module test(i_clk, i_reg, o_reg, o_wire);
-input i_clk;
-input i_reg;
-output o_reg;
-output o_wire;
-
-// Enable this to see how it doesn't fail on yosys although it should
-//reg o_wire;
-// Enable this instead of the above to see how logic can be mapped to a wire
-logic o_wire;
-// Enable this to see how it doesn't fail on yosys although it should
-//reg i_reg;
-// Disable this to see how it doesn't fail on yosys although it should
-reg o_reg;
-
-logic l_reg;
-
-// Enable this to tst if logic-turne-reg will catch assignments even if done before it turned into a reg
-//assign l_reg = !o_reg;
-initial o_reg = 1'b0;
-always @(posedge i_clk)
-begin
-  o_reg <= !o_reg;
-  l_reg <= !o_reg;
-end
-
-assign o_wire = !o_reg;
-// Uncomment this to see how a logic already turned intoa reg can be freely assigned on yosys
-//assign l_reg = !o_reg;
-
-sub_mod sm_inst (
-  .i_in(1'b1),
-  .o_out(o_reg)
-);
-endmodule
-
diff --git a/tests/various/reg_wire_error.sv b/tests/various/reg_wire_error.sv
new file mode 100644
index 000000000..ab461b95a
--- /dev/null
+++ b/tests/various/reg_wire_error.sv
@@ -0,0 +1,40 @@
+module sub_mod(input i_in, output o_out);
+assign o_out = i_in;
+endmodule
+
+module test(i_clk, i_reg, o_reg, o_wire);
+input i_clk;
+input i_reg;
+output o_reg;
+output o_wire;
+
+// Enable this to see how it doesn't fail on yosys although it should
+//reg o_wire;
+// Enable this instead of the above to see how logic can be mapped to a wire
+logic o_wire;
+// Enable this to see how it doesn't fail on yosys although it should
+//reg i_reg;
+// Disable this to see how it doesn't fail on yosys although it should
+reg o_reg;
+
+logic l_reg;
+
+// Enable this to tst if logic-turne-reg will catch assignments even if done before it turned into a reg
+//assign l_reg = !o_reg;
+initial o_reg = 1'b0;
+always @(posedge i_clk)
+begin
+  o_reg <= !o_reg;
+  l_reg <= !o_reg;
+end
+
+assign o_wire = !o_reg;
+// Uncomment this to see how a logic already turned intoa reg can be freely assigned on yosys
+//assign l_reg = !o_reg;
+
+sub_mod sm_inst (
+  .i_in(1'b1),
+  .o_out(o_reg)
+);
+endmodule
+
diff --git a/tests/various/reg_wire_error.ys b/tests/various/reg_wire_error.ys
new file mode 100644
index 000000000..b9d03155d
--- /dev/null
+++ b/tests/various/reg_wire_error.ys
@@ -0,0 +1 @@
+read_verilog -sv reg_wire_error.sv