From: lkcl <lkcl@web>
Date: Sat, 30 Apr 2022 15:39:52 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2537
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=80dee5b03b0dedc50c6e81c59c0f6211828f5028;p=libreriscv.git

---

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index 849ae216d..0f55c1128 100644
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -944,16 +944,7 @@ required.*
         uint64_t l;
     } el_reg_t;
 
-    bw(elwidth):
-        if elwidth == 0: return xlen
-        if elwidth == 1: return 8
-        if elwidth == 2: return 16
-        // elwidth == 3:
-        return 32
-
-    get_max_elwidth(rs1, rs2):
-        return max(bw(int_csr[rs1].elwidth), # default (XLEN) if not set
-                   bw(int_csr[rs2].elwidth)) # again XLEN if no entry
+    elreg_t int_regfile[128];
 
     get_polymorphed_reg(reg, bitwidth, offset):
         el_reg_t res;
@@ -969,10 +960,8 @@ required.*
         return res
 
     set_polymorphed_reg(reg, bitwidth, offset, val):
-        if (!int_csr[reg].isvec):
-            # sign/zero-extend depending on opcode requirements, from
-            # the reg's bitwidth out to the full bitwidth of the regfile
-            val = sign_or_zero_extend(val, bitwidth, xlen)
+        if (!reg.isvec):
+            # not a vector: first element only, overwrites high bits
             int_regfile[reg].l[0] = val
         elif bitwidth == 8:
             int_regfile[reg].b[offset] = val
@@ -983,25 +972,18 @@ required.*
         elif bitwidth == 64:
             int_regfile[reg].l[offset] = val
 
-      maxsrcwid =  get_max_elwidth(rs1, rs2) # source element width(s)
-      destwid = int_csr[rs1].elwidth         # destination element width
+An example ADD operation with predication and element width overrides:
+
       for (i = 0; i < VL; i++)
         if (predval & 1<<i) # predication uses intregs
-           // TODO, calculate if over-run occurs, for each elwidth
-           src1 = get_polymorphed_reg(rs1, maxsrcwid, irs1)
-           // TODO, sign/zero-extend src1 and src2 as operation requires
-           if (op_requires_sign_extend_src1)
-              src1 = sign_extend(src1, maxsrcwid)
-           src2 = get_polymorphed_reg(rs2, maxsrcwid, irs2)
+           src1 = get_polymorphed_reg(RA, srcwid, irs1)
+           src2 = get_polymorphed_reg(RB, srcwid, irs2)
            result = src1 + src2 # actual add here
-           // TODO, sign/zero-extend result, as operation requires
-           if (op_requires_sign_extend_dest)
-              result = sign_extend(result, maxsrcwid)
-           set_polymorphed_reg(rd, destwid, ird, result)
-           if (!int_vec[rd].isvector) break
-        if (int_vec[rd ].isvector)  { id += 1; }
-        if (int_vec[rs1].isvector)  { irs1 += 1; }
-        if (int_vec[rs2].isvector)  { irs2 += 1; }
+           set_polymorphed_reg(RT, destwid, ird, result)
+           if (!RT.isvec) break
+        if (RT.isvec)  { id += 1; }
+        if (RA.isvec)  { irs1 += 1; }
+        if (RB.isvec)  { irs2 += 1; }
 
 
 # Twin (implicit) result operations