From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 7 Jun 2018 05:00:44 +0000 (+0100)
Subject: corrections
X-Git-Tag: convert-csv-opcode-to-binary~5256
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=80e996a9d28784cb5c3c14e7c35a46af9c0d8cb1;p=libreriscv.git

corrections
---

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index fd803bddc..43b49ff84 100644
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -60,7 +60,7 @@
  \begin{itemize}
    \item Extremely powerful (extensible to 256 registers)\vspace{10pt}
    \item Supports polymorphism, several datatypes (inc. FP16)\vspace{10pt}
-   \item Requires a separate Register File (16 w/ext to 256)\vspace{10pt}
+   \item Requires a separate Register File (32 w/ext to 256)\vspace{10pt}
    \item Implemented as a separate pipeline (no impact on scalar)\vspace{10pt}
   \end{itemize}
   However...\vspace{10pt}
@@ -145,7 +145,7 @@
   Note: EVERYTHING is parallelised:
    \begin{itemize}
    \item All LOAD/STORE (inc. Compressed, Int/FP versions)
-   \item All ALU ops (soft / hybrid / full HW, on per-op basis)
+   \item All ALU ops (Int, FP, SIMD, DSP, everything)
    \item All branches become predication targets (C.FNE added?)
    \item C.MV of particular interest (s/v, v/v, v/s)
    \item FCVT, FMV, FSGNJ etc. very similar to C.MV