From: lkcl <lkcl@web>
Date: Sat, 4 Jun 2022 21:49:20 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1962
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8106464b532751b8961a51b3bb0e8f745b681676;p=libreriscv.git

---

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index f7117b08e..2a47bd463 100644
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -56,7 +56,8 @@ Comparative instruction count:
 * ARM SVE2: around 1,000 instructions, prerequisite: SVE
 * Intel AVX-512: around 4,000 instructions, prerequisite AVX2 etc.
 * RISV-V RVV: 192 instructions, prerequisite 96 Scalar RV64GC instructions
-* SVP64: **four** instructions, prerequisite SFS (150) or
+* SVP64: **four** instructions, 24-bit prefixing of
+  prerequisite SFS (150) or
   SFFS (214) Compliancy Subsets
 
 # Major opcodes summary