From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 23 Nov 2019 01:23:51 +0000 (-0800)
Subject: Constant driven signals are also an input to submodules
X-Git-Tag: working-ls180~778^2~21
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8119383f8198d621e88b54fdd615e352ecc576bb;p=yosys.git

Constant driven signals are also an input to submodules
---

diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc
index 707bc26b3..a1fac9b79 100644
--- a/passes/hierarchy/submod.cc
+++ b/passes/hierarchy/submod.cc
@@ -33,7 +33,7 @@ struct SubmodWorker
 	CellTypes ct;
 	RTLIL::Design *design;
 	RTLIL::Module *module;
-	pool<Wire*> outputs;
+	pool<Wire*> constants, outputs;
 
 	bool copy_mode;
 	std::string opt_name;
@@ -125,7 +125,7 @@ struct SubmodWorker
 			RTLIL::Wire *wire = it.first;
 			wire_flags_t &flags = it.second;
 
-			if (wire->port_input)
+			if (wire->port_input || constants.count(wire))
 				flags.is_ext_driven = true;
 			if (wire->port_output || outputs.count(wire))
 				flags.is_ext_used = true;
@@ -235,6 +235,14 @@ struct SubmodWorker
 				outputs.insert(c.wire);
 			}
 		}
+		for (auto wire : module->wires()) {
+			auto sig = sigmap(wire);
+			for (auto c : sig.chunks()) {
+				if (c.wire)
+					continue;
+				constants.insert(wire);
+			}
+		}
 
 		if (opt_name.empty())
 		{