From: Brian Paul <brianp@vmware.com>
Date: Thu, 9 Apr 2009 01:35:24 +0000 (-0600)
Subject: i965: set BRW_MASK_DISABLE flag in "send" instruction in brw_dp_READ_4()
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8131123effd2124b8ca2aad04bf543e2fe82c7b0;p=mesa.git

i965: set BRW_MASK_DISABLE flag in "send" instruction in brw_dp_READ_4()

This fixes the random results that were seen when fetching a constant
inside an IF/ELSE clause.  Disabling the execution mask ensures that all
the components of the register are written.
---

diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 21ce8369db4..220c3afb150 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -978,9 +978,10 @@ void brw_dp_READ_4( struct brw_compile *p,
    {
       struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND);
    
-      insn->header.predicate_control = 0; /* XXX */
+      insn->header.predicate_control = BRW_PREDICATE_NONE;
       insn->header.compression_control = BRW_COMPRESSION_NONE; 
       insn->header.destreg__conditonalmod = msg_reg_nr;
+      insn->header.mask_control = BRW_MASK_DISABLE;
   
       /* cast dest to a uword[8] vector */
       dest = retype(vec8(dest), BRW_REGISTER_TYPE_UW);