From: lkcl <lkcl@web>
Date: Fri, 6 May 2022 20:04:50 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2360
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=813fa97ed223daf96ead6e1cfc76779a6548bb37;p=libreriscv.git

---

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index de6a2eaa0..80dad52b4 100644
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -689,4 +689,17 @@ much easier for the main CPU to take over in the event that PEs are
 currently occupied.  Plus, the twin lessons that inventing ISAs, even
 a small one, is hard (mostly in compiler writing) and how complex
 GPU Task Scheduling is, are being heard loud and clear.
-
+Put another way:
+
+* if the PEs run a foriegn ISA, then the Basic Blocks embedded inside
+  the ZOLC Loops must be in that ISA **OR**
+* In order that the main CPU can execute the same sequence if necessary,
+  the CPU must support dual ISAs: Power and PE **OR**
+* There must be a JIT binary-translator which either turns PE code
+ into Power ISA code or vice-versa **OR**
+* The compiler dual-compiles the original source code, and embeds
+  both a Power binary and a PE binary into the ZOLC Basic Block
+
+All of these would work, but it is simpler and a lot less work
+just to have the PEs
+execute the exact same ISA (or a subset of it).